module testbench;
reg CLK;
reg RST;
reg WFLAG;
wire [11:0] ADDR;
wire [31:0] XDATA;

DUMMY_ROM DUMMY_ROM(
    .CLK(CLK),
    .RST(RST), 
    .ADDR(ADDR),
    .XDATA(XDATA),
    .WFLAG(WFLAG)
);

DUMMY_ADDR DUMMY_ADDR(
    .CLK(CLK),
    .RST(RST),
    .XADDR(ADDR)
);

parameter STEP = 10;

always #(STEP / 2) CLK = ~CLK;

initial begin
  $dumpfile("wave.vcd");
  $dumpvars(0, testbench);
  $monitor ("%t: CLK = %b, RST = %b , ADDR = %h, XDATA = %h", $time, CLK, RST, ADDR, XDATA);
  CLK = 0;
  RST = 0;
  WFLAG = 0;
  #10
  RST = 1;
  #10
  #100
  WFLAG = 1;
  #20
  $finish;
end

endmodule


//ファイルに読み込み・書き込みするROM
module DUMMY_ROM(CLK, RST, ADDR, XDATA, WFLAG);
input CLK;
input RST;
input WFLAG;
input [11:0] ADDR;
output [31:0] XDATA;
reg [31:0]ROM[0:9];
reg [31:0] XDATA;
initial $readmemh("test.hex", ROM);

always @(posedge CLK)
  begin
    if (~RST)
      XDATA <= 32'h0;
    else if (WFLAG)
      $writememb("dump.bin", ROM, 2, 3);
    else
      XDATA <= ROM[ADDR];
  end

endmodule

//ROMアドレス生成
module DUMMY_ADDR(CLK, RST, XADDR);
input CLK;
input RST;
output [11:0]XADDR;
reg [11:0]XADDR;
always @(posedge CLK)
  begin
    if (~RST)
      XADDR <= 12'h0;
    else if (XADDR == 12'ha)
      XADDR <= 12'h0;
    else
      XADDR <= XADDR + 1;
  end
endmodule


//以下はtest.hexの内容
0_0_0_0_0_0_0_0
0_0_0_0_0_0_0_1
0_0_0_0_0_0_0_2
0_0_0_0_0_0_0_3
0_0_0_0_0_0_0_4
0_0_0_0_0_0_0_5
0_0_0_0_0_0_0_6
0_0_0_0_0_0_0_7
0_0_0_0_0_0_0_8
0_0_0_0_0_0_0_9