module testbench;
reg CLK;
reg RST;
wire [7:0]INA;
wire [15:0]XOUT;
reg START_FLAG;

parameter CK = 10;

initial begin
  #0   CLK = 0;
  #0   RST = 0;
  #50 RST = 1;
end

initial begin
  forever begin
    #(CK * 0.5) CLK = ~CLK;
  end
end
reg END_FLAG;

always @(END_FLAG) begin
  $finish;
end

reg [31:0] R_INA;
reg [31:0] CNT;

initial begin
  wait(!RST);
   START_FLAG = 1;
end

always @(posedge CLK) begin
  if (~RST) begin
    R_INA <= 0;
    CNT <= 0;
  end  else if (START_FLAG) begin
    R_INA <= $random;
    CNT <= CNT + 1'h1;
  end else begin
    R_INA <= R_INA;
    CNT <= CNT;
  end
  
end

always @(posedge CLK) begin
  if (CNT == 32)
    END_FLAG <= 1;
end

assign INA = R_INA[7:0];


initial begin
  $dumpfile("wave.vcd");
  $dumpvars(0, testbench);
  $monitor("time(%t) CLK = %b, RST = %b, CNT = %d", $time, CLK, RST, CNT);
end

TEST TEST(
          .CLK(CLK),
          .RST(RST),
          .INA(INA),
          .XOUT(XOUT)
          );




endmodule

module TEST(CLK, RST, INA, XOUT);
input CLK;
input RST;
input [7:0] INA;
output [15:0] XOUT;
reg [15:0] XOUT;

always @(posedge CLK) begin
  if (~RST)
    XOUT <= 16'h0;
  else
    XOUT <= {INA, 1'b0};
end

endmodule