module testbench;

reg CLK;
reg RST;
reg [31:0] MEM[0:9];
reg [31:0] INDATA;
wire [3:0] XDATA;
parameter STEP = 10;
parameter MAX_CNT = 100;
integer i;

initial begin
  forever begin
  #(STEP * 0.5) CLK = ~CLK;
  end
end
initial begin
  $dumpfile("wave.vcd");
  $dumpvars(0, testbench);
  $readmemh("data.hex", MEM);
  #0 CLK = 1;
  #0 RST = 0;
  #10 RST = 1;
end

test test(
    .CLK(CLK),
    .INDATA(INDATA),
    .RST(RST),
    .XDATA(XDATA)
    );

initial begin
  repeat(MAX_CNT) begin
    #STEP;
  end
  for (i = 0; i < 10; i = i + 1) begin
    #1 INDATA <= MEM[i];
  end
end

always @(posedge CLK)
  if (XDATA == 4'ha) begin
    $finish;
  end


endmodule



module test(CLK, RST, INDATA, XDATA);
input CLK;
input RST;
input [31:0] INDATA;
output [3:0] XDATA;
reg [3:0] XDATA;

always @(posedge CLK) begin
  if (~RST) XDATA <= 4'h0;
  else      XDATA <= INDATA[3:0];
end


endmodule

//以下はdata.hexの内容
0_0_0_0_0_0_0_1
0_0_0_0_0_0_0_2
0_0_0_0_0_0_0_3
0_0_0_0_0_0_0_4
0_0_0_0_0_0_0_5
0_0_0_0_0_0_0_6
0_0_0_0_0_0_0_7
0_0_0_0_0_0_0_8
0_0_0_0_0_0_0_9
0_0_0_0_0_0_0_a