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for文
プログラミング言語のfor文と同等。但しverilogでは、モジュール直下に配置する事はできない。
(書式)
for(初期化式; 条件式; 反復式) begin
//処理
end
タスクはモジュール内で定義する。また、タスクの処理内でalwaysは使用できない。
for文の例
module testbench;
reg CLK;
reg RST;
reg [31:0] MEM[0:9];
reg [31:0] INDATA;
wire [3:0] XDATA;
parameter STEP = 10;
integer i;
always #(STEP / 2) CLK = ~CLK;
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testbench);
#0 CLK = 1;
#0 RST = 0;
#10 RST = 1;
$readmemh("data.hex", MEM);
end
test test(
.CLK(CLK),
.INDATA(INDATA),
.RST(RST),
.XDATA(XDATA)
);
initial begin
for (i = 0; i < 10; i = i + 1) begin
//遅延させる
#20 INDATA <= MEM[i];
end
end
always @(posedge CLK)
if (XDATA == 4'ha)
$finish;
endmodule
module test(CLK, RST, INDATA, XDATA);
input CLK;
input RST;
input [31:0] INDATA;
output [3:0] XDATA;
reg [3:0] XDATA;
always @(posedge CLK) begin
if (~RST) XDATA <= 4'h0;
else XDATA <= INDATA[3:0];
end
endmodule
//以下はdata.hexの内容
0_0_0_0_0_0_0_1
0_0_0_0_0_0_0_2
0_0_0_0_0_0_0_3
0_0_0_0_0_0_0_4
0_0_0_0_0_0_0_5
0_0_0_0_0_0_0_6
0_0_0_0_0_0_0_7
0_0_0_0_0_0_0_8
0_0_0_0_0_0_0_9
0_0_0_0_0_0_0_a
while文
プログラミング言語のwhile文と同等。但しverilogでは、モジュール直下に配置する事はできない。iniatial文やalways文の中で利用できる。
while文の例
module testbench;
reg CLK;
reg RST;
reg [31:0] MEM[0:9];
reg [31:0] INDATA;
wire [3:0] XDATA;
parameter STEP = 10;
reg ENB;
integer i;
always #(STEP / 2) CLK = ~CLK;
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testbench);
$readmemh("data.hex", MEM);
#0 CLK = 1;
#0 RST = 0;
#0 ENB = 0;
#10 RST = 1;
#100 ENB = 1;
end
test test(
.CLK(CLK),
.INDATA(INDATA),
.RST(RST),
.XDATA(XDATA)
);
initial begin
while(~ENB) begin
#STEP;
end
for (i = 0; i < 10; i = i + 1) begin
#1 INDATA <= MEM[i];
end
end
always @(posedge CLK)
if (XDATA == 4'ha) begin
$finish;
end
endmodule
module test(CLK, RST, INDATA, XDATA);
input CLK;
input RST;
input [31:0] INDATA;
output [3:0] XDATA;
reg [3:0] XDATA;
always @(posedge CLK) begin
if (~RST) XDATA <= 4'h0;
else XDATA <= INDATA[3:0];
end
endmodule
//以下はdata.hexの内容
0_0_0_0_0_0_0_1
0_0_0_0_0_0_0_2
0_0_0_0_0_0_0_3
0_0_0_0_0_0_0_4
0_0_0_0_0_0_0_5
0_0_0_0_0_0_0_6
0_0_0_0_0_0_0_7
0_0_0_0_0_0_0_8
0_0_0_0_0_0_0_9
0_0_0_0_0_0_0_a
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