module testbench;
reg CLK;
reg RST;
reg[31:0] INA;
wire[31:0] XOUT;
parameter STEP = 10;

initial begin
  CLK = 0;
  RST = 0;
  INA = 1;
  #10 RST = 1;
  forever begin
    #(STEP * 0.5) CLK = ~CLK;
  end
end

AAA AAA(
        .CLK(CLK),
        .RST(RST), 
        .INA(INA),
        .XOUT(XOUT)
       );
integer i;
reg [9:0] j;
reg end_flag;
initial begin
  $dumpfile("wave.vcd");
  $dumpvars(0, testbench);
  @(end_flag);
  $finish;
end
//以下はbreak
/*
initial begin
  @(posedge RST);
  begin : BREAK //break効果
  for (i = 1; i < 20; i = i + 1) begin
    @(posedge CLK)
    INA = i;
    if (i == 10) disable BREAK;
  end
  end
  end_flag = 1;
end
*/

//以下はcontinue
initial begin
  @(posedge RST);
  for (j = 1; j < 20; j = j + 1) begin : CONTINUE
    @(posedge CLK)
    if (j[0] == 1'b0) disable CONTINUE;
    INA = j;
  end
  end_flag = 1;
end

endmodule

module AAA(CLK,RST,INA,XOUT);
input CLK;
input RST;
input[31:0] INA;
output[31:0] XOUT;
reg[31:0] XOUT;
wire[31:0] W_OUT;
assign W_OUT = {INA[30:0], 1'b0};
always @(posedge CLK) begin
  if (~RST)
    XOUT <= 0;
  else
    XOUT <= W_OUT;
end

endmodule